用一片CPLD芯片就完成了全部的译码、时序控制、显示控制等功能，这样CPU和LCD之间就可能直接用一个CPLD芯片连接了，无需再加入其它的接口器件。
Realizing all needed function such as encoding, sequence control, display control and so on with only one CPLD chip, it can be used to connect CPU with LCD without any other devices.
自启动预载接口芯片以控制为主，时钟关系复杂。时序设计是整个设计的重点和难点。
Interface and download chip is control-oriented and has complex clock relationships, therefore timing design is the key and difficult point.
并着重研究了系统的硬件设计，讨论了CPLD的时序控制、图像传感器的寄存器控制以及DSP芯片的硬件开发、软件实现、实验分析等等。
We put emphasis upon systemic hardware design, discuss the sequence control of CPLD, Register control of image sensor, and hardware exploiture, software realization, empirical analysis of DSPs, etc.
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