首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。

Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.

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本文提出了产生数字电路测试码的一种算法——主路径敏化法。

This paper presents an algorithm of test patterns generation for digital circuits which is called the principal path sensitization method.

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