提出了分数倍抽样率转换器的高效时变网络结构的设计方法，并用现场可编程门阵列(FPGA)实现。

The design method for the efficient time-varying network architecture of the fractional multiple sampling rate converter is presented and its field programmable gate array (FPGA) is implemented.

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抽样率是指模拟声音每秒钟被计算机转换成二进制数字的次数。

The sampling rate is the number of times per second analog sound is turned into a binary number by the computer.

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