数字高清晰度电视信道接收芯片实现中使用了基于扫描链的可测试设计和静态验证技术。
In the project of HDTV channel receiving ASIC, DFT techniques based on scan-chains, STA (Static Timing Analysis) and formal verification has been adopted.
不同于以往基于单个芯核扫描链平衡的调度技术，本文提出的对平衡调度技术是利用两个芯核配对后扫描链可能比单个芯核扫描链更平衡，获得比单平衡更短的测试时间。
This paper presents a novel test scheduling solution, unlike previous techniques that take advantage of balanced scan chains of every single core, utilizing the balance of pairwise combined cores.
一种基于扫描链阻塞技术的扫描测试结构被提出来，该结构有效地降低了测试功耗，但其测试应用时间较长。
A scan test scheme based on scan chain disabling technique has been proposed, which can effectively reduce test power. However, its test application time is long.
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