...；低功耗设计；多时钟系统；哈佛结构；流水线结构 [gap=709]Key Word: microcontroller; low power design; multi-clock system; Ha Vard structure; under pipeline ...
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异步fifo的设计方案对于多时钟系统中异步接口电路的设计具有一定的参考价值。
The asynchrony FIFO module can be applied in the other asynchrony interface circuit design in multi-clock system.
带两个或更多时钟域的系统是测试过程变复杂。
Systems with two or more clock domains complicate the testing process.
多时钟实现方法在项目管理与其它类别微处理器系统级设计中的运用给予了拓展性描述。
Expanded description on project management and other MCUs' system - level architecture is also discussed in this paper.
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