本文给出一个时序逻辑电路的多故障测试模拟程序。
This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.
针对数字电路中多故障测试生成效率较低的问题，提出了基于神经网络的数字电路多故障测试生成算法。
A multiple faults test generation algorithm based neural networks for digital circuits is proposed considering that the test generation efficiency for multiple faults in digital circuits is low.
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