...研究 - docin.com豆丁网 gn RuleCheck,DRc)、电气规则检查(ElectricalRule Check,ERC)和版图验证(LayoutversusSchematics,LVS)等。设计者可以 从互连线电容的降低和时钟树的综合两个方面入手来降低电路的功耗。
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... docin.com豆丁网 gn RuleCheck,DRc)、电气规则检查(ElectricalRule Check,ERC)和版图验证(LayoutversusSchematics,LVS)等。设计者可以 从互连线电容的降低和时钟树的综合两个方面入手来降低电路的功耗。
基于1个网页-相关网页
而集成电路的后端设计包括了版图设计和验证,它们不在本论文的讨论范围之内。
The back-end design includes layout design and verification, but they will not be discussed in this paper.
课题着重对这两个模块的电路结构以及版图结构进行了深入的研究和分析,并采用SPICE工具进行了模拟验证。
The paper has an emphatical discussion on the study and analysis of the circuit structure and layout structure of these two modules, and makes a lot of SPICE simulation and verification.
介绍了VLSI版图验证中电阻提取的基本原理和主要方法,给出了一种新颖的基于边界元法的电阻提取算法。
The basic theory of resistance extraction in VLSI layout verification is described. A novel resistance extractor based on the boundary element method is presented.
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