为了提高总体系统速度，可采用硬件触发同步系统中的所有仪器。
To increase overall system speed, synchronize all the instruments in the system using hardware triggers.
设计了二进制树型拓扑结构传播统一的系统时钟和触发信号，采用CPLD提供传感器间的精确时序和同步。
A binary tree routing topology is designed for propagating the system clock and trigger signal and the accurate timing and synchronization between sensors are provided by CPLD.
锁相环路是完成两个电信号相位同步的反馈控制系统，适宜于变流装置的同步触发电路之中。
The phase lock loop is a feedback control system that makes two telecommunication signals' phase synchronization, suitable to the synchronous trigger circuit of the convertor device.
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