同时，其鉴频鉴相算法表达式简单，易于用可编程数字器件实现。
The frequency and phase detection module is very easy to realize by programmable digital devices.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
针对检测数字图像灰度梯度的最大值法，采用SOBEL边缘检测算子对数字图像进行边缘检测，并利用硬件(大规模可编程逻辑器件CPLD)实现了数字图像的边缘提取。
The article will contrapose maximum value method based on detecting image grey grad, and take example of SOBEL operator to realize digital image fringe picking up based on hardware (CPLD).
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