硬件性能是可变的，它依赖显示适配器和驱动程序，而软件性能是固定的。
Hardware capabilities are variable, depending on the display adapter and driver, while software capabilities are fixed.
为降低低密度奇偶检验码译码的硬件实现复杂度，提出了一种可变步长均匀量化“和积”译码算法。
A variable step uniform quantization(VSUQ) sum-product algorithm(SPA) was developed to reduce the hardware complexity of low-density parity-check(LDPC) code decoding.
其运算量仅为基于梯度的可变形块匹配算法（GB-DBMA）的一半，但能得到更好的主客观预测质量，且更易于VLSI硬件实现。
NS-DBMA has only half computation amount of the gradient-based search algorithm (GB-DBMA) but gets better subjective and objective quality, and is much easier to implement by VLSI.
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