... very-fast-front overvoltage 陡波前过电压 Very-fast Hardware Description Language 利用硬件描述语言 He Drove Very Fast 他开车开很快 ...
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介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
该抢答器单元电路的软件设计分别利用原理图设计、硬件描述语言设计完成。
The circuit software was designed using schematic diagram and hardware description language (VHDL) respectively.
利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
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