文章提出的新型乘法累加器，具有在不同模式下分别处理16位与32位数据，或16位与32位数据混合运算能力。
The multiply-accumulate unit (MAC) specified in this paper describes a novel architecture. It can handle operation of 16-bit and 32-bit separately or mixed operation of them in different modes.
在乘法和除法运算中，用作累加器扩充的一种寄存器。
A register used as an extension of the accumulator during multiply and divide processes.
应用推荐