提出了一种新的低功耗非冗余排序总线编码方法，通过对改进的偏移地址线的动态重排以降低具有高负载的地址总线的功耗。
The irredundant sorting bus encoding method reduces the power dissipation of highly capacitive memory address bus based on the dynamic reordering of the modified offset address bus lines.
地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。
The address bus is used by the processor to select aspecific memory location or register within a particular peripheral.
一旦你开始调整GTL ref电压(单独针对每个核心数据和地址总线)你将会发现不同的总线频率需要不同的电压组合。
Once you begin adjusting GTLREF voltages (for each core data and address bus) you will find that different bus frequencies respond differently to variations in the voltage.
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