模拟信号采集模块和数字信号采集模块是本系统与外部信号的接口。

Aanalog signals acquisition module and digital signals acquisition module are the interface between the system and the external signals.

youdao

在电路设计过程中，对后级接口电路进行了最优化设计，采用VHDL描述的方式实现了低压数字延时电路模块的设计。

In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.

youdao

为了提高数字信号处理速度，现在一些实现专用算法的DSP模块和通信接口也由FPGA或者CPLD实现。

In order to improve digital signal processing speed, dedicated algorithm to achieve some of the DSP and communication interface module also realized by the CPLD or FPGA.

youdao