要避免任何数与 0 相除或溢出，将所有除法转换为乘法并检查运算符号（Y2=Y1 的水平线不会计入算法）

To avoid any division by zero or overflow, transform all division into multiplication and check for the sign (horizontal lines with Y2=Y1 do not count in the algorithm)

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我们对到a变为1为止所经历的除法、乘法的次数以及总共经历的步数感兴趣。

We are interested in the number of divisions, multiplications, and total number of steps until a reaches 1.

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在FPGA乘法器资源相同的条件下，采用最优结构设计的接收机内部fir滤波器阶数比直接实现形式高了近4倍。

With the same number of multipliers in FPGA, the order of FIR filter in receiver with above optimum structure is nearly4 times than it implemented in direct way.

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