The clock generator and output encode circuit is given. The pipeined interpolating A/D converter is fabricated and measured.
给出了时钟产生电路和输出编码电路等数字电路结构,对该流水插值A/D转换器进行了投片测试。
参考来源 - 高速低功耗A/D转换器及相关技术研究·2,447,543篇论文数据，部分数据来源于NoteExpress
According to the encode demands of different stage resolution, clock-control encode circuit is designed.
根据不同级精度的编码要求，设计出时钟控制编码电路。
The selection and use of encode and decode circuit simplify the system circuit and improve the reliability of wireless data transmission.
编码解码电路的选择及巧妙运用，简化了电路，提高了无线数传的可靠性。
应用推荐