This paper gives a design of high AD sampling based on FPGA,the high sampling clock based on FPGA and the configured chips of AD95164 and ADC by FPGA. Effective Number Of Bits(ENOB) of the sampling result are measured.
本文提出基于FPGA的高速AD采样设计,给出了基于FPGA的高速采样时钟设计方案以及FPGA对时钟芯片AD95164与ADC的配置设置,并对采样结果有效位数进行测定。
参考来源 - 基于FPGA的高速AD采样设计·2,447,543篇论文数据,部分数据来源于NoteExpress
以上来源于: WordNet
应用推荐