4.2.4 边沿触发器(Edge-triggered Flip-flop) 袍秘攻袄劝嘣汁皆缟犰役充芈捏湿堡公仿父谊删甍韫 为了提高触发器的可靠性,增强抗干扰能力,希望触 发器的次态仅仅决于CP信号...
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Low power double edge-triggered flip-flop 计画低功率之双缘触发型正反器
jk edge-triggered flip-flop jk边沿触发器
Single-edge-triggered Flip-flop 单边沿触发器
double edge triggered flip flop 双边沿触发器
double-edge-triggered flip-flop 双沿触发器
Edge-triggered D flip-flop 边沿触发D触发器
ecl double-edge-triggered d flip-flop ecl双边沿d触发器
The application of this type of double-edge-triggered flip-flop in seq…
文章还介绍了该双边沿触发器在时序电路中的应用。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider.
提出了一种基于共振隧穿二极管的新型边沿触发d触发器并将之用于构成二进制分频器。
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