Based on a method of 2 dimension data rearrange, a high speed and high efficiency implementation of DRAM access is proposed in the design of block buffer manager.

在数据块缓冲管理器的设计中，采用一种基于二维数据重排的访问方式，实现高速高效的DRAM访问。

youdao

Power-hungry parts see even more of a boost: they can carry Iris Pro graphics with embedded DRAM, which should double the 3D speed on H-series mobile chips (47-55W of typical power) and triple it for the R-series (around 65-84W) on the desktop.

ENGADGET