提供高速度动态内存控制器(DRAM Controller)的设计，适用各种高速DRAM，如Double Data Rate (DDR) SDRAM、RAMBUS等设计。
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The refresh cycles are usually performed by a peripheral called a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
Thee refresh cycles are usually performed by a peripheral called a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
Then, when the external reset signal is disabled, a delayed reset signal DLYRST is generated and applied to the DRAM controller so that it is reset.
然后，当使外部复位信号无效时，生成一个延迟的复位信号并将其加到DRAM控制器以将其复位。
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