all digital phase locked loop 全数字锁相环 ; 全数位式锁相回路
Half-Digital Phase Locked Loop 半数位式相锁回路 ; 半数位式锁相回路
all-digital phase-locked loop 全数字锁相环
digital phase-locked loop [电子] 数字锁相环
digital phase locked loop cir 数字锁相环电路
all digital phase-locked loop 全数字式锁相环
DPLL digital phase-locked loop 数字相位锁相环路
Lead-lag digital phase-locked loop 超前
An all digital phase locked loop based on FPGA is presented.
介绍了当前广泛应用的数字锁相环的原理和基于FPGA的设计方法。
参考来源 - 基于FPGA的数字锁相环的研究与实现·2,447,543篇论文数据，部分数据来源于NoteExpress
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.
设计了一种用于通信系统载波同步的新数字锁相环。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
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