Data is loaded into the KVp digital to analog converter on A4 and A8.
这个数据会被载入A4和A8区的数模转换器。
The real time processing of high speed data flow makes strict demands on the performance of descendant digital down converter in the wideband digital receiver.
在宽带数字接收机中，高速数据流的实时处理对后继数字下变频器性能提出了极为苛刻的要求。
It consists of a digital controller, SRAM for display data memory, a DC-DC voltage converter, reference current generators, a pre-charge voltage generator, 64 common drivers, and 132 segment drivers.
芯片内部主要包括数字控制器，显示数据存取器，DC - DC电压转换器，参考电流产生器，电压预充电路产生器，64个行驱动电路和132个列驱动电路。
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