Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges.
每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic.
这款双通道adc内核采用多级、差分流水线架构，并集成了输出纠错逻辑。
Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges.
每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。
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