This thesis mainly focuses on design and implement of baseband module of CR experimental system and research on reduction of PAPR.
本文的主要工作是CR实验系统的基带模块的设计与实现以及降低峰均比技术的研究。
In the chapter of design and implement of real time storage system, we put forward the design idea based on the computer high performance bus.
实时存储系统的设计与实现一章,提出基于计算机高性能总线结构的实时存储设计思想。
This thesis does research on the key module of Q-switch driver—high efficiency Class-E power amplifier, including the design and implement of the prototype.
本文主要研究了声光Q开关驱动器的关键模块——高效率E类功率放大器,设计实现了工程样机。
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