The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).
高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。
The controller is modeled as a hierarchical finite-state-machine from which a behavioral VHDL description is generated automatically. The device is prototyped using a FPGA-based emulating system.
首先将该控制器模拟为一个分级有限状态机，通过它自动生成一个VHDL行为描述，然后使用基于FPGA的仿真系统模拟这个控制器。
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