Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.

深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。

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In deep submicron era, IC design in physical design has more and more challenge, with the increasing design scale, faster clock frequency and minimizing process dimension.

在深亚微米时代，随着设计规模变大，时钟频率越来越高以及工艺尺寸的减小，IC物理设计面临着诸多困难。

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Familiar with deep submicron process design rule.

熟悉深亚微米工艺设计规则。

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