The CLB bus is a kind of on-chip system bus which is usually used to connect IPs with high speed and high data width.
CLB总线是一种片上系统总线,一般用来连接高速度、高数据宽度的IP。
A data width of 0 and a total width of 8 would indicate that the memory is solely used to provide error correction bits.
值为0的数据宽度以及总宽度为8表示该内存只用于提供错误纠正位。
A microprocessor consisting of bit slice operates at such high speed and has such an extremely flexible logic structure that its data width can be easily defined and changed.
用位片器件构成的微处理器速度高,逻辑结构极为灵活,可以十分简便地规定和改变字长。
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