configurations data input module 结构数据输入模组
The FPGA-based implementation of data input module and data output module of VLBI standard interface is expatiated in this dissertation.
本文主要阐述基于FPGA实现VLBI标准接口数据输入模块和数据输出模块。
Chapter 5 and 6 are the realization of data input module and data output module, which includes module partition, inner structure of submodules and the timing relationship of main signals.
第五章和第六章分别阐述了数据输入模块和数据输出模块的具体实现，包括模块划分、子模块的内部结构以及主要信号之间的时序关系。
This article looks at the implementation of sets of tests of module interfaces; testing that for some specified input data, a particular response is obtained.
本文介绍模块接口测试集的实现；测试对某一指定的输入数据，是否获取特定的响应。
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