But it causes the problem of memory access wait cycle.

但随之带来了访问内存时出现等待周期的问题。

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Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle.

另一个独特的构架特性是内存系统，它允许一个取指，并在同一时间，每一个核可以读取数据在每一个单独的时钟周期内。

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