Currently main acceleration mechanisms include multi-processor acceleration, ASIC acceleration, custom instruction based on configurable CPU, coprocessor (FPGA/DSP) acceleration etc.
当前主要的加速机制包括多核处理器加速、专用集成电路(ASIC)加速、基于可配置处理器的定制指令加速、协处理器加速(如FPGA/DSP等)等。
参考来源 - 定制指令与协处理器加速机制的研究·2,447,543篇论文数据，部分数据来源于NoteExpress
Both had custom instruction sets, with programs designed in their raw machine code.
通过在其原型机代码中设计的程序，两者都自定义了指令集。
Vega processors included a custom read barrier instruction that included bit field checking in reference metadata as well as special virtual memory protection for GC-compacted pages.
Vega处理器包含了一个客户化的读屏障指令，它具有字段检查元数据和针对GC压缩页面的特殊的虚拟内存保护。
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