This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP.
本文设计了一款面向16位定点DSP芯片的三阶电荷泵锁相环。
参考来源 - DSP芯片中的锁相环研究与设计The circuit using standard CMOS CPPLL structure, including Phase Frequency Detector(PFD), Charge Pump(CP), Low Pass Filter(LPF), Voltage Controlled Oscillator(VCO) and Frequency Divider(Divider) five modules.
电路采用标准的CMOS电荷泵锁相环结构,包括鉴频鉴相器(PFD)、电荷泵(CP)、低通滤波器(LPF)、压控振荡器(VCO)和分频器(Divider)五个模块。
参考来源 - 微机械陀螺中锁相环电路设计·2,447,543篇论文数据，部分数据来源于NoteExpress
This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP.
本文设计了一款面向16位定点DSP芯片的三阶电荷泵锁相环。
So the formula is very adapt to the systematic design and early verification of 3 rd Order CPPLL.
非常适合于电荷泵锁相环（ CPPLL）的系统级设计和前期验证。
The noise model CPPLL frequency synthesizer is also established in order to provide theory of designing high order, low noise and high performance CPPLL frequency synthesizer.
同时，建立了电荷泵锁相环频率合成器噪声模型，为高阶、低噪声电荷泵锁相环频率合成器的设计提供理论依据。
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