...成电路的锁相环时钟发生器,他是一款基于0.18 μm CMOS 数字工艺设计的高频电荷泵锁相环（Charge Pump Phase Locking Loop,CPPLL）,最高输出频率达1.2 GHz。
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This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP.
本文设计了一款面向16位定点DSP芯片的三阶电荷泵锁相环。
参考来源 - DSP芯片中的锁相环研究与设计The circuit using standard CMOS CPPLL structure, including Phase Frequency Detector(PFD), Charge Pump(CP), Low Pass Filter(LPF), Voltage Controlled Oscillator(VCO) and Frequency Divider(Divider) five modules.
电路采用标准的CMOS电荷泵锁相环结构,包括鉴频鉴相器(PFD)、电荷泵(CP)、低通滤波器(LPF)、压控振荡器(VCO)和分频器(Divider)五个模块。
参考来源 - 微机械陀螺中锁相环电路设计·2,447,543篇论文数据，部分数据来源于NoteExpress
This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP.
本文设计了一款面向16位定点DSP芯片的三阶电荷泵锁相环。
The noise model CPPLL frequency synthesizer is also established in order to provide theory of designing high order, low noise and high performance CPPLL frequency synthesizer.
同时，建立了电荷泵锁相环频率合成器噪声模型，为高阶、低噪声电荷泵锁相环频率合成器的设计提供理论依据。
Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL (Charge-pump PLL) has become one of the major digital PLL product.
电荷泵锁相环具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点，成为了当前数字锁相环产品的主流。
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