Thus, the interface design of multi-DSP and CPCI bus with FPGA and bridge chip PCI9656 is described in detail.
本文详细介绍如何通过FPGA和桥接芯片pci9656实现多dsp与CPCI总线的接口设计。
The data transfer rate between varied boards in radar signal processors based on VME or CPCI bus was limited by the bus rate.
在基于VME总线或CPCI总线的雷达信号处理机中，板与板之间的数据传输速率受限于总线的速率。
CPCI bus Interface Standard: CPCI bus is a high performance industrial bus acceptable for 3u and 6u board design based on the PCI bus specification.
CPCI总线接口标准的研究：CPCI总线是以pci总线规范为基础的高性能工业总线，适用于3u和6u插板的设计。
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