The gate count of a system based on ERCCL can be significantly reduced, which, in turn, will decrease the energy loss.

所以一个基于ERCCL的系统可以大大减少逻辑门数，从而降低系统能耗。

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Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.

采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。

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Adding parallelism typically increases gate count, but the improved computational efficiency allows for the lower clock frequency needed to meet real-time constraints.

添加并行一般通过门数增加来实现，但提高计算效率要求降低时钟频率以满足实时需求。

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