The factors which will be encountered are descried and modules include anti-aliasing filter, clock circuit, band gap voltage reference, sc integrator, latched comparator and DAC are designed.
最后在考虑实际因素的基础上，依次设计了时钟产生电路、前置滤波器、带隙基准源、开关电容积分器、锁存比较器和DAC等子模块电路并做了仿真。
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