All circuits are designed by HDL and can be intergrated in one CPLD or FPGA chip, used in the frame synchronization and timing of digital communications receiver.
全部电路由硬件描述语言实现，可以集成在一片CPLD或FPGA芯片内部，用于数字通信系统接收端的帧同步和定时。
BAE Systems will develop a new radar warning receiver prototype that can identify radio frequency and communications activity in real time.
BAE系统公司将开发一种新型雷达预警接收机原型，该原型能实时识别无线电频率和通信活动。
In data communications, the transmission by a receiver of acknowledge characters as an affirmative response to a sender.
数据通信中，由接收方向发送方传送应答字符作为肯定回答的传输过程。
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