Although awkward, it is balanced as a common clock and its mechanisms work perfectly.

也许有点奇怪，但是它能和普通的钟表一样保持平衡，而且它的内部机械运转正常。

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This Design Idea describes how to implement a common clock (synchronous version) for an FPGA-based FIFO for data-width conversion with different-width read and write data ports.

本设计方案描述了为不同宽度读写数据端口的数据宽度转换，怎样基于FPGA的FIFO实现共有时钟(同步)。

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