clock code position 钟点位置
clock code 时间码
clock phase-code 锁存码值
CLK Pulse Code Modulation Clock 脉冲编码调制时钟
PCMCLK Pulse Code Modulation Clock 脉冲编码调制时钟
PCM-CLK Pulse Code Modulation Clock 脉冲编码调制时钟
The direct digital synthesis (DDS) is adopted to generate the pseudo-random code clock having high precision and stability.
利用直接频率合成技术产生高精度、高稳定度的扩频伪码时钟。
The default time, which is retrieved from the system clock of the machine the code is running on, is used most of the time.
默认时间,即从运行代码的机器的系统时钟检索到的时间,在大部分情况下被使用。
For years, processor makers consistently delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification.
多年来,处理器制造厂商在不断提高时钟速度和指令级并行性,因此单线程代码不需要修改就可在新的处理器上更快运行。
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