Clock Tree Synthesis 时钟树综合 ; 时钟树合成 ; 时钟树生成
clock tree balance 时钟树平衡
Clock tree generation 产生时钟树
low power clock tree synthesis 低功耗时钟树综合
Bounded-Skew Clock Tree 有界偏差时钟树
clock-tree 时钟树
Top Clock tree 顶层时钟树
clock tree layout 时钟布图
clock tree latency 时钟树延时
In the thesis, we make a deep research on the key technology in ASIC backend design, such as Floorplan, Power-supply distributed design, Clock Tree Synthesis, NanoRouting, Layout Verification.
深入研究了布局规划、电源网络分配、时钟树综合、详细布线以及物理验证等后端设计关键技术。
参考来源 - 基于ASIC实现雷达信号处理芯片的后端设计By using auto placement and routing, the floorplan, clock tree synthesis, placement and routing were achieved. Finally, the asynchronous FIFO of the PCI interface controller was accomplished.
利用自动布局布线工具完成芯片的顶层规划、插入时钟树、布局和布线,最终完成用于PCI接口芯片的异步FIFO设计。
参考来源 - 用于PCI接口芯片的异步FIFO设计·2,447,543篇论文数据，部分数据来源于NoteExpress
And the clock tree synthesis is the most critical factor in timing closure.
本论文对时钟树综合中的几个最关键问题进行深入研究。
The correct test results of the chip also verify the effectiveness of this clock tree synthesis program.
芯片测试结果的正确也验证了这种时钟树综合方案的有效性。
In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
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