Clock Tree Synthesis 时钟树综合 ; 树合成 ; 时钟树合成 ; 时钟树生成
clock tree balance 时钟树平衡
Clock tree generation 产生时钟树
low power clock tree synthesis 低功耗时钟树综合
Bounded-Skew Clock Tree 有界偏差时钟树
clock-tree 时钟树
Top Clock tree 顶层时钟树
clock tree layout 时钟布图
In the thesis, we make a deep research on the key technology in ASIC backend design, such as Floorplan, Power-supply distributed design, Clock Tree Synthesis, NanoRouting, Layout Verification.
深入研究了布局规划、电源网络分配、时钟树综合、详细布线以及物理验证等后端设计关键技术。
参考来源 - 基于ASIC实现雷达信号处理芯片的后端设计By using auto placement and routing, the floorplan, clock tree synthesis, placement and routing were achieved. Finally, the asynchronous FIFO of the PCI interface controller was accomplished.
利用自动布局布线工具完成芯片的顶层规划、插入时钟树、布局和布线,最终完成用于PCI接口芯片的异步FIFO设计。
参考来源 - 用于PCI接口芯片的异步FIFO设计·2,447,543篇论文数据，部分数据来源于NoteExpress
And the clock tree synthesis is the most critical factor in timing closure.
本论文对时钟树综合中的几个最关键问题进行深入研究。
In order to reduce the power in the clock tree, a new gating circuit is presented.
为了能够减少时脉系统的功率消耗，一种新型的闸电路被提出。
According to the requirement of BTB's design, the paper adopts the symmetrical clock tree technique.
针对BTB的设计要求，确定采用树状网络分布的时钟分布技术。
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