Therefore, how to design a high efficient and high stable clock subsystem is a significant problem.
因此，如何设计出一个高效、高稳定性的时钟子系统成为摆在工程师面前一个头等重要的问题。
The capacity and speed of the memory subsystem in this architecture can be improved using the existed memory devices while the cost can be downgraded without enhancement of the clock frequency.
该结构可利用现有存储器件在不增加时钟频率的情况下，提高存储器系统的容量和速度，同时降低成本。
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