This paper studies the ADC measuring clock jitter technology based on simple interference sampling.
本文基于简单相干采样法研究了ADC测量时钟抖动的技术。
参考来源 - 高速时钟信号抖动的ADC测量技术研究Because ring oscillator achieves high stability and low clock jitter output signal, it is always selected.
而环形振荡器由于其能够获得稳定度高、低抖动时钟输出信号,且易于片上集成,从而成为时钟发生器的首选。
参考来源 - 片上时钟产生电路的研究·2,447,543篇论文数据，部分数据来源于NoteExpress
Pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.
像素时钟输出频率范围从10mhz到140mhz的采样250ps的峰峰值抖动。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
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