打盹（Doze）：主处理器和汇流排交换器都停止，透过对时脉控制器（clock controller）模组的预先设定，一些特定的周边也能在此模式时自动的关掉时脉供给。此模式的恢复运作时间很短。
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Reset Clock Controller 复位与时钟控制器
RICC Reset Interrupt Clock Controller 重新设置中断时钟控制器
system clock controller 系统时钟控制器
Clock Pulses Controller 时钟脉冲控制器
clock actuated controller 时钟驱动信号控制器
The whole design is described in VHDL. By logic optimization, the controller has an advantage of less resource utilization and less clock delay compared with other similar controllers.
整个设计采用VHDL语言描述，经过逻辑优化，该显示控制器有着比同类控制器占用资源少、时钟延迟小等优点。
This paper introduces the functions and work principles of serial clock chip DS1302, the design of interface circuit with AT89C51 single -chip microcomputer in the spray irrigation controller.
本文介绍了串行时钟芯片DS1302的功能和工作原理，并给出ds1302在灌溉控制器中与AT 89 C 51单片机的接口电路设计。
Secondly, controller design of NCS for delay compensation is studied when the controller is clock-driven.
其次，研究了控制器为事件驱动时网络控制系统的时延补偿控制。
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