Clock Buffer 时钟缓存 ; 时钟缓冲器
Global Clock Buffer 全局时钟缓冲
delay controllable clock buffer 延时可控时钟网络驱动器
delay-controllable clock buffer 时延可控时钟网络驱动器
System clock recover is the key in digital TV system. The paper proposes a scheme of clock settlement based on buffer technology from researching DTV receiving system.
系统时钟恢复是数字电视系统设计中的难点。从研究数字电视接收系统出发，根据实际需要深入探讨并提出了一种基于缓存技术的系统时钟处理方案。
The protocol realized some functions, such as two-way data buffer, shift register, clock circuit and parity check.
在通信协议中，主要实现了双向数据缓冲器、数据移位寄存器、时钟控制电路以及奇偶校验等功能。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
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