clock recovery based 时钟恢复系统
PLL Based Clock Generator 时钟发生器及支持产品
GPS based clock synchronizer 全球定位系统授时单元
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计,并通过数码管驱动电路动态显示计时结果。
A kind of GPS satellite synchronous clock based on the DS80C320 High-speed SCM is recommended in the following thesis, to solve problem mentioned above.
针对这种情况,本文设计了一种基于DS80C 320高速单片机的GPS卫星同步时钟。
This thesis has proposed a designing schema of embedded network synchronization clock based on NTP, having done the entire development of hardware and software system.
本论文提出嵌入式ntp网络同步时钟源的设计方案,完成了整个系统的硬件和软件开发。
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