The time correction error of substation clock synchronization, the clock precision of automation equipment and the time correction interval are quantitatively analyzed.
定量分析了变电站时钟同步的校时误差、自动化装置时钟精度及基于两者的校时时间间隔确定等问题。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
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