If the circuit under verification is carved out from the design, the input waveforms to the circuit must be configured to be identical to them when the circuit is embedded in the design.

如果被验证的电路是从设计中勾画出的，那么电路的输入波形必须被配置为与当电路被嵌入到设计中时的一样。

youdao

The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.

LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。

youdao

Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.

验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。

youdao