FPGA placement and routing is the most time-consuming stage in chip design. To design faster, smaller size, less delay, and low-power algorithm is a very hot research topic.

布局布线是FPGA芯片设计中最耗时的阶段，能够设计出更加快速、更小面积、时延少、低功耗的算法是学术界研究的热点和趋势。

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The fragmentation of resource placement is a critical factor to affect CU (Chip Utilization) and TRR (Task Rejection Ratio) in the field of reconfigurable computing.

在可重构计算领域，布局硬件任务所产生的碎片是影响系统资源利用率和任务拒绝率的关键因素之一。

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