Having summarized top-down design flow of modern integrated circuit,this paper gives the design of the system parameters of charge pump phase locked loop(PLL) frequency synthesizer from the perspective of system.
在归纳总结现代集成电路Top-Down的设计流程的基础上,从系统的角度出发,提出电荷泵锁相环频率合成器系统参数的设计方法。
参考来源 - CMOS锁相环频率合成器系统设计·2,447,543篇论文数据，部分数据来源于NoteExpress
In this dissertation, theory, model, design and implementation of charge pump phase locked loop frequency synthesizer are lucubrated.
本文围绕电荷泵频率合成器的理论、模型、设计和实现，进行了深入的研究。
A novel multi-layer Charge-Pump Phase-Locked Loop (CP-PLL) behavioral model is presented in this paper.
提出了一种全新的电荷泵锁相环的行为级建模方法。
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