buried channel transistor 埋沟晶体管
depletion mode N-channel transistor 耗尽模N型沟道晶体管
fin flip-flop actuated channel transistor 鳍式正反器致动通道电晶体
p-channel transistor p沟晶体管
buried d channel transistor 埋沟晶体管
recess channel array transistor 凹槽阵列晶体管 ; 凹道排列晶体管
induced-channel type transistor 感应沟道型晶体管
field-effect-transistor channel 场效应晶体管沟道
transistor channel 电晶体通道
A semiconductor device structure (10) uses two semiconductor layers (16 & 20) to separately optimize N and P channel transistor carrier mobility.
一种半导体器件结构(10),其使用两个半导体层(16&20)以 分别优化N和P沟道晶体管载流子迁移率。
They then defined the transistor channel using electron-beam lithography, removing graphene outside of channel regions with an oxygen plasma.
然后在氧等离子体中用电子束刻蚀法去除沟道区石墨烯形成晶体管的沟道。
The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof.
本发明提供一种薄膜晶体管及其制造方法,其中该晶体管的沟道的 基本长度被缩短以微型化半导体装置。
应用推荐