Identify problems with memory, including low buffer pool hit ratios, catalog cache hit ratios, and package cache hit ratios.

识别内存问题，包括较低的缓冲池命中率、较低的目录缓存命中率和较低的包缓存命中率。

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TLB cache entry reuse (cache hit) equates to quicker address translation and subsequently faster access to physical memory.

tlb缓存条目重用(缓存命中)意味着更快的地址转换，还意味着对物理内存的更快的访问。

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Because workloads with high Symmetrix cache read-hit rates are serviced at memory access speed, storing the data needed on EFDs may not result in a significant increase in performance.

因为具有高symmetrix缓存读中率的工作负载都是以内存访问速度实现的，所以在EFD中存储所需要的数据可能不会对性能有大的改进。

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